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CLA90000 Series
High Density CMOS Gate Arrays
DS5500
ISSUE 2.0
April 1997
INTRODUCTZarlinkION
The CLA90000 family of gate arrays from Zarlink Semiconductor consists of 14 fixed-size arrays with the option of building optimized arrays with up to 1.1 million gates. This family offers low-power, mixed voltage capability and a high density silicon architecture. The CLA90000 series is easy to use with and without synthesis tools and comes with design utilities to provide customers with a faster time to market.
BENEFITS
I Fast Customer Time To Market - Direct sign-off on industry standard CAE tools - Comprehensive industry-standard design tool flows - SystemBuilderTM megacell libraries - Worldwide design centre support - Reliable prototype and production delivery - Two silicon sources I Cost-effective solutions - Optimized silicon architecture for excellent silicon utilization - Statistical process control for optimum yield - High quality and reliability, manufactured to MIL STD 883 methods and other industry recognized standards
FEATURES
I Low power, 0.5W/MHz/gate at 3V supply (NAND 2 loads) I High density of 5,425 available gates/mm2 I 3V and 5V I/O capability on the same device I 150ps gate delay for 2-input NAND with two loads (5V) I Accurate delay modelling for gates and tracks with sign off quality CAE design libraries for QuickSim II and Verilog-XL I CAD libraries optimized for synthesis I Up to 512K available gates and 352 pads with fixed arrays I Up to 1.1M available gates and 520 pads with optimized arrays I Double or triple layer metal on a 0.6m (drawn) process I Operation from 2.7V to 5.5V I Methodologies for low clock skew I Phase locked loop cells, both gate array variant and embedded variant with on-chip filter I Embedded RAM and ROM I Expanding range of Zarlink SytemBuilder soft and hard cells for complex functions including 85C30, 8051, and 8251 devices I Wide range of packaging options including Ball Grid Arrays I Commercial and military pad density options
OVERVIEW
The CLA90000 series product has a number of important elements that assist designers. Ease of design Ease of design is an important feature of this new product, as shown by the checking and verification utilities built into the Zarlink design kits. Accurate simulation is essential for good design, and the Zarlink 5th order pin to pin delay model algorithms help ensure first time success. Various design routes and industry-standard systems are available. Cell Libraries Cell libraries are optimized for synthesis and include a complete range of soft and hard macros. Cells include basic logic, oscillators, JTAG controllers and macros from the extensive SystemBuilderTM library such as microprocessors, memories, UARTs, and DSP elements, which improve time to market through a shorter design cycle. Embedded custom blocks can be inserted into a gate array to produce dense memory or other compact high performance components. Optimized arrays can offer gate array cycle times if embedded blocks are defined early in the design cycle.
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Silicon and process This generation of gate arrays uses a 0.6m process and meets its primary objectives of dense architecture and low power without compromising performance. Packing density is 5,500 available gates per mm2, with utilization for three-layer metal typically exceeding 70% (random logic). Power consumption is low with both 5V and 3V supplies, reaching 0.5W/MHz/gate at 3V with two gate loads. Service The service Zarlink offers to customers encompasses product guidance from a marketing team, engineering expertise, including design advice and in-depth knowledge of CAE tools, through to fast delivery and world class quality and reliability standards.
A wide range of packages is offered for both the fixed and optimized arrays, and all arrays offer the choice of commercial or military pad density. The lower pad density meets the need of MIL STD customers in terms of bond wire spacing specifications. CLA90000 has a range of fixed array bases to offer a suitable array size for most applications, from low to high volume.
Fixed Gate Arrays
Typical Utilization of Gates 2-layer metal 9700 14000 26000 33000 42000 63000 75000 102000 117000 134000 151000 169000 188000 230000 3-layer metal 15000 23000 40000 52000 66000 99000 117000 160000 183000 208000 235000 263000 293000 358000 Number of Pads Low# 44 52 64 72 80 96 104 120 128 136 144 152 160 176 264 Low# High 84 100 128 144 160 192 208 240 256 272 288 304 320 352 520 High
Array
No. of Gates
ARRAY SIZES
CLA90000 consists of a series of fixed, embedded and optimized arrays that can be combined as shown below.
CLA 901 CLA 902 CLA 903 CLA 904 21632 32768 57800 75272 95048 141512 168200 228488 262088 297992 336200 376712 419528 512072
Fixed arrays
Embedded memory or macros
CLA 905
Optimized arrays
CLA 906 CLA 907 CLA 908 CLA 909 CLA 910
Standard, fixed array sizes are prefabricated and appropriate probe cards are available for fast turn around and low cost. For a design with a large memory (2k bits or more) or when an embedded macro like an ARM RISC microprocessor is required, all device layers can be fabricated. An embedded array uses the fixed array bases but with a section of the array removed to make space for the custom block. Optimized arrays are customized to the application, can be built with the required number of pads or gates, and can also include embedded cells. Optimized arrays are most often used in medium- to highvolume applications where the larger engineering cost is balanced by lower production pricing. For high volume devices, an optimized array can be generated at Zarlink using automated tools. The Zarlink Design Centres can advise on the best options, in terms of fixed gate arrays and standard cells, for a given design. Embedded and optimized arrays are as easy to design with as the fixed array bases, and have similar prototyping times provided custom cell definition or new array size is decided early in the design.
CLA 911 CLA 912 CLA 913 CLA 914
Optimized Gate Arrays
Max. No. of Gates Typical Utilization of Gates 2-layer metal 517000 3-layer metal 804000 Max. Number of Pads
Array
*CLA9XX
114912 8
* optimized arrays available up to 1.1M gates. # MIL density pad spacing
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Choosing an Array
To find the most suitable array for an application, refer to the array table on the left and find the smallest one that has enough pads, remembering to look at the correct pad density column and to include power and ground pads. If the array has enough gates, the design is `pad limited', and will have spare gates. If the design needs more gates, and therefore a bigger array, it is `gate limited' and will have spare pads. An additional consideration is the number of I/O pins that can be tested by automatic test equipment. The locally based Zarlink Design Centre will help resolve any testing issues. If a design is pad limited, it requires the smallest array with sufficient pads. Two-layer metal (CLA prefix) is generally the most economical. If the selection process arrives at a gate limited design, it requires the smallest array with sufficient usable gates and three-layer metal (CLT prefix) will generally be lower cost. Also, if a special clock or power distribution scheme is required, three layer metal is often needed.
I/O ARRANGEMENT
I I/O cell options for 3V and 5V supply I 3V and 5V I/O on the same device I Slew rate control on outputs I Excellent ESD protection to 3kV and good latch-up immunity to 200mA, meets STACK 0001 V12.1 and MIL STD 883 I PCI /PC Card fully compatible I/Os A wide range of I/O cells is available, and each one has three forms to suit 3V, 5V, or mixed 3 and 5V operation. Also, each I/O cell can be individually configured as one of the following: * * * * * * * * Input Output Tristate output Open drain output Open source output Bidirectional Open drain bidirectional Open source bidirectional
ARCHITECTURE
I Compact routable core cell I Typical design reduced in silicon area by up to 50% over the previous gate array generation I Utilization from 45% to 80% for triple-layer metal, depending on design topology I Efficient register file RAM (3 gates/bit) I Custom full layer (embedded) RAM option for larger memories The gate array core cell was chosen after researching a number of different cell layouts. The core cell contains four transistors, two NMOS and two PMOS. These are built as one structure with a shared central source/drain region with the polysilicon gates independently available. This core cell layout gives efficient metal interconnections for a range of logic gates, flip-flops, and register file RAM, and also permits over-cell routing to increase gate utilization.
The I/O stage has a number of components used to construct a wide variety of I/O cells, including pullup and pulldown resistors and small transistors for oscillators. 5V cells are available with TTL or CMOS compatible input Schmitt circuitry. 3V cells meet both TTL and CMOS specifications. The CLA90000 has four separate internal supply rails: one for the core, one for the buffer, and two for output areas of the chip. The buffer supply rail is completely isolated for very low noise. This offers the benefit of good noise immunity with multiple supply voltage capability to suit the application. The mixed 3 and 5V I/O capability can be used for power saving or interfacing with 3V and 5V systems. Slew rate control is provided within the I/O output drive circuitry to minimize switching noise transients. This is a useful feature in larger designs, particularly where multiple high drive outputs switch simultaneously. It also reduces reflections from unterminated pc board tracks. Electrostatic discharge (ESD) protection is built into the input and output cells, and has been designed to withstand in excess of 3kV (human body model). The structure and process is also highly resistant to latch-up and able to withstand forward bias currents in excess of 200mA.
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CLOCK AND POWER DISTRIBUTION
I Low clock skew distribution strategies I Power grid to minimize voltage drop
Power Distribution and Estimation
The Zarlink layout methodology constructs grids for all array size options, including optimized arrays. This grid can use metal layers one and two for horizontal and vertical grids, and metal layer three may also be used on some larger arrays. Methods of implementation are available for use with flat layout, manual methods, or hierarchy. A simplified grid arrangement is shown below. In addition the CLA90000 series of arrays is supported by EPIC PowerMill power estimation software (check availability)..
It is known in the industry that large, complex designs working at high speed are vulnerable to problems associated with poor clock and power distribution. The following sections indicate how the Zarlink design and layout methodology avoids these problems.
Optional horizontal metal-3 grid
Clock Distribution
Zarlink has experience with a variety of layout methods to prevent clock skew problems. The preferred method is to use built-in clock grid generation and drive the clock grids with buffers distributed throughout the chip, which limits skew to below 70ps and provides a reliable solution to clock distribution suitable for most designs. For all clock strategies, post-layout clock delays are extracted and fed back for resimulation. An example of one clock distribution method is illustrated below.
Vertical metal-2 gr
Pads
Pad Ring
Local clock grid Subcircuit
Figure 2 Power Grid
MANUFACTURING
I Class 10 clean room I Advanced equipment including mini-environments and SMIF box transportation between processes I Statistical process control (SPC) monitoring of all stages I Vibration-free for reliable manufacture I Two silicon sources The CLA90000 product is manufactured near Plymouth, England in a purpose-built vibration-free factory for submicron process geometries. The factory uses the latest automated equipment for 8-inch wafers in class 10 clean room conditions with SMIF boxes for semi-automatic handling. Computer aided manufacture ensures production efficiency and the lowest possible defect level. In addition to the world class wafer fabrication facility, the probe and final test areas are equipped with the latest analog and digital testers. Zarlink Semiconductor is committed to continuous investment to provide state-of-the-art CMOS ASICs. A qualified second source for this silicon process is available.
Global clocks
Figure 1 Example Clock Distribution
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DESIGN SUPPORT
I Flexible design routes I Proven right first time design I Local design support Design and layout support for the CLA90000 arrays is available from many local centres worldwide, each connected to our headquarters via high speed data links. A design centre engineer, as part of the Zarlink support team, is assigned to each customer circuit to give full assistance with all aspects of the design and to ensure a smooth and efficient design flow. Zarlink offers both customer and turnkey design routes, to allow for varying types of customer interface while maintaining our responsibility to ensure first time working devices. The design process incorporates a design audit procedure to verify compliance with customer specification and to ensure manufacturability. The procedure includes three review meetings with the customer held at key stages of the design. This is illustrated in the diagram on the next page. Design review one: Held at the beginning of the design cycle to check and agree on performance, packaging, specifications and design timescales. Held after logic simulation but prior to layout to ensure satisfactory functionality, timing performance, and adequate fault coverage. Held after layout and post-layout simulation verification of satisfactory design performance after insertion of actual track loads. Final check of all device specifications before prototype manufacture.
CAE Support
I Synthesis with Synopsys, Mentor or Cadence I Sign-off simulation with Mentor or Cadence I VIEWlogic VCS simulator supported I VITAL compliant library I Full top-down design flow support I Point tools supported, including Zycad and Powermill I Direct route to layout and test I Advanced delay modelling and netlist checking It is Zarlink policy to fully support industry-standard CAE systems that enable a customer to sign off their design without resimulation on a golden simulator. This has the benefit to the customer of not having to learn new tools, and to use the tools they prefer and are familiar with. There is no overhead in engineering effort or time taken rechecking simulation results. Zarlink offers libraries for synthesis tools such as Synopsys, Mentor Autologic II, and Cadence Synergy. This allows a full hierarchical or top-down approach to logic design. The Zarlink Universal Delay Compiler (UDC) is supplied with all design kits for advanced delay modelling and comprehensive netlist checking. The UDC matches Synopsys and Mentor native delay calculation. The advanced features of the synthesis and simulation tools are used for nonlinear delay modelling for better simulation accuracy. This is implemented for optimum speed depending on the particular tool. Other advanced features are supported where they are available. The information supplied by the customer in the approved CAE vendor format is used as a direct input to the tools that perform the layout and generate the test program.
Design review two:
Design review three:
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SOFTWARE TOOLS
Concept Assessment
RESPONSIBILITY CUSTOMER
DESIGN REVIEW 1
Design capture/compilation or synthesis Improve testability
CUSTOMER AND Zarlink
Testability analysis
INDUSTRY STANDARD DESIGN SOFTWARE AND Zarlink LIBRARIES
Functional simulation
Correct design errors
CUSTOMER OR Zarlink
Test vectors simulation
Improve testability
Zarlink VERIFICATION TOOLS
Zarlink
Netlist handover
DESIGN REVIEW 2 Zarlink OR INDUSTRYSTANDARD LAYOUT TOOLS INDUSTRYSTANDARD SOFTWARE
Place and route Netlist modification
CUSTOMER AND Zarlink
CUSTOMER OR Zarlink
Post-layout simulation
DESIGN REVIEW 3
Prototype manufacture
CUSTOMER AND Zarlink
Zarlink CUSTOMER AND Zarlink Zarlink
APPROVAL
Production
Figure 3 Design Flow
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ADVANCED DELAY MODELLING
I Edge speed modelling I Pin to pin timings I Nonlinear delay modelling I Accurate delay derating
THERMAL MANAGEMENT
I Lower power CMOS for improved thermal management I 0.5W/MHz/gate (3V supply 2-input NAND with 2 loads) I Software constructed power grids for efficient power distribution I Copper lead frame QFPs for lower thermal resistance I High pinout power packages available The increase in speed and density available through advanced CMOS processes results in a corresponding increase in power dissipation. Semicustom designers now have the ability to design circuits in excess of half a million usable gates, and chip power consumption is an important issue. To meet the requirements of high speed, high gate count designs, Zarlink CLA90000 arrays offer low power factors and a selection of power packages for improved thermal management.
Pin to Pin Delays
Delay models use times between individual input and output pins for both rising and falling delays, as illustrated below.
A B C F
Figure 4 Delay Paths The use of individual pin to pin delays, e.g. A to F and B to F, improves simulation accuracy as there can be considerable variation in delay between different input pins. For complex gates (e.g. AND-NOR gates or adders) the variation is up to 40%. For simple NAND and NOR logic gates the typical variation is 20%.
QUALITY AND RELIABILITY
I Statistical process control used in manufacture I Regular sample screening and reliability testing I Screening to MIL and other recognized standards is available At Zarlink, quality and reliability are built into the product by statistical control of all processing operations and by minimizing random uncontrolled effects in all manufacturing operations. Process management involves full documentation of procedures with recording of batch by batch data using computerized WIP tracking systems. A common information management system is used to monitor the manufacturing of Zarlink CMOS processes and operations. All products benefit from the use of this integrated monitoring system resulting in the highest quality standards for all technologies. Further information and reliability results are contained in the Quality MOS Brochure, available from Zarlink Sales Offices.
Nonlinear Curve Fitting
For fast input edges (0.5ns) delay time increases linearly with the output load, whereas for high output loads delay increases linearly with edge speed. Delays for slow input edges and light input loads do not follow the linear model, so a simple linear model cannot represent delays accurately. A more complex formula, which includes interaction between edge and load factors, is used to model delays for CLA90000.
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DERATING FOR VOLTAGE PROCESS AND TEMPERATURE
The following figures show how gate delay increases as supply voltage is reduced.
Temperature Derating
Note that it is important to use the junction and not the ambient temperature for worst-case simulations.
Derating Factor
3
2.5 2
Derating Factor
2.15 2.40 2.65 2.70 3.00 3.30 3.60 4.50 5.00 5.50
1.4 1.3 1.2 1.1 1 0.9
1.5 1 0.5
Voltage
Figure 5 Derating for a 5V supply (5V normalised to 1)
0.8 0.7 -55 -40 0 25 70 85 100 125 150
Temperature (C)
1.6 Figure 7 Temperature Derating
Derating Factor
1.4 1.2 1 0.8 0.6 0.4 2.15 2.40 2.65 2.70 3.00 3.30 3.60 4.50 5.00 5.50
Voltage
Figure 6 Derating for a 3V supply (3V normalised to 1)
Process Derating
Speed slow typical fast
Derating Factor 1.58 1.00 0.62
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AC ELECTRICAL CHARACTERISTICS
For the CLA90000 series, one load unit (LU) is 17fF.
Example delays for 5V only I/O (ns)
Outputs 50pF 12mA bistate 68 fF (4LU) 0.23 0.11 0.16 0.12 0.26 0.09 0.55 0.41 tpHL tpLH Inputs 34fF (2 LU) 0.45 0.70 68fF (4 LU) 0.48 0.72 24mA bistate tpLH tpHL tpLH tpHL 2.87 3.58 100pF 2.93 3.61 100pF 4.11 4.22 200pF 4.17 4.26
Typical Microcell Delays (ns) (25C, 0.2ns input edge)
Gates 34 fF (2LU) INVX1 tpLH tpHL NAND2X2 tpLH tpHL NOR2x2 tpLH tpHL SDF tpLH tpHL 0.24 0.12 0.18 0.15 0.31 0.10 0.81 0.61 3V 68 fF (4LU) 0.34 0.17 0.23 0.19 0.41 0.13 0.91 0.67 34 fF (2LU) 0.16 0.09 0.13 0.10 0.20 0.07 0.49 0.37 5V
Typical I/O Delays (25C, 0.2ns input edge)
I/O delays depend on the voltage of the device, i.e. all 5V I/O, all 3V I/O, or mixed 3V and 5V I/O. The tables below give example delays for each of these cases.
Example delays for 3V only I/O (ns)
Outputs 50pF tpLH 6mA bistate tpHL 4.72 100 pF 12mA bistate tpLH tpHL 4.26 4.75 5.66 200 pF 6.30 5.68 4.16 100pF 6.20
Inputs 34fF (2 LU) tpLH tpHL 0.88 1.29 68fF (4 LU) 0.93 1.31
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DC ELECTRICAL CHARACTERISTICS Example delays for mixed 3V and 5V I/O (ns)
Delays for mixed 3 and 5V I/O are not the same as for single voltage designs because of level shifting stages.
Absolute Maximum Ratings
Parameter Min. -0.5 -0.5 -0.5 Max. 7.0 VDD+0.5 VDD+0.5 4 Units V V V kV
3V I/O in a mixed 3V and 5V I/O design
Outputs 50pF tpLH 6mA bistate tpHL 4.72 100pF 12mA bistate tpLH tpHL 4.25 4.75 5.66 200pF 6.29 5.68 4.16 100pF 6.20
Supply voltage Input voltage Output voltage Static discharge voltage (HBM) Storage temperature Ceramic Plastic
-65 -55
150 150
C C
Exceeding the absolute maximum ratings may cause permanent damage to the device. Extended exposure at the maximum ratings will affect device reliability. HBM stands for Human Body Model.
Inputs 68fF tpLH tpHL 0.79 0.82 0.82 136fF
Normal Operating Conditions
Parameter 0.86 Supply voltage Input voltage Output voltage Outputs Current per pad 50pF 12mA bistate tpLH tpHL 4.01 3.68 100pF 24mA bistate tpLH tpHL 4.14 3.74 100pF 5.25 4.33 200pF 5.38 4.39 Junction temperature Ceramic package Plastic package Ambient temperature Commercial grade Industrial grade Military grade 0 -40 -55 70 85 125 C C C -55 -55 +150 +125 C C 2.7 VSS VSS 5.5 VDD VDD 100 V V V mA Min. Max. Units
5V I/O in a mixed 3V and 5V I/O design.
Inputs 34fF tpLH tpHL 0.45 0.70 0.48 0.72 68fF
Neither performance nor reliability is guaranteed outside these limits. Extended operation above these limits may affect device reliability.
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Input Switching Thresholds
All characteristics are for temperatures between -55 and 150C (junction temperature).
Value Characteristic Symbol Min. CMOS Schmitt - CS Input low voltage Input high voltage Hysteresis TTL Schmitt - TS Input low voltage Input high voltage Hysteresis Low voltage Schmitt - BS/NS Input low voltage Input high voltage Hysteresis Low voltage Schmitt - BS/NS Input low voltage Input high voltage Hysteresis VIL VIH VH 2.2 100 0.2VDD VIL VIH VH 2.0 300 0.2VDD VIL VIH VH 2.0 300 0.8 VIL VIH VH 0.7VDD 400 0.2VDD Typ. Max.
Unit
Conditions
4.5 VDD 5.5V V V mV 4.5 VDD 5.5V V V mV 2.7 VDD 3.3V V V mV 3.0 VDD 3.6V V V mV
Note: CS cells are 5V CMOS compatible, TS cells are 5V TTL compatible and all other cells are 3V compatible.
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Output Voltages and Currents
All characteristics are for temperatures between -55 and 150C (junction temperature).
Characteristic
Symbol Min.
Value Typ. Max.
Unit
Conditions
High output voltage All outputs 01N 02N 03N 06N 12N Low output voltage All outputs 01N 02N 03N 06N 12N High output voltage All outputs 01N 02N 03N 06N 12N Low output voltage All outputs 01N 02N 03N 06N 12N VOL VOL VOL VOL VOL VOL VSS+0.05 0.2 0.2 0.2 0.2 0.2 0.4 0.4 0.4 0.4 0.4 V V V V V V VOH VOH VOH VOH VOH VOH 0.8VDD 0.8VDD 0.8VDD 0.8VDD 0.8VDD VDD-0.05 0.9VDD 0.9VDD 0.9VDD 0.9VDD 0.9VDD V V V V V V VOL VOL VOL VOL VOL VOL VSS+0.05 0.2 0.2 0.2 0.2 0.2 0.4 0.4 0.4 0.4 0.4 V V V V V V VOH VOH VOH VOH VOH VOH 0.8VDD 0.8VDD 0.8VDD 0.8VDD 0.8VDD VDD-0.05 0.9VDD 0.9VDD 0.9VDD 0.9VDD 0.9VDD V V V V V V
2.7 VDD 3.6V IOH = -1A IOH = -0.5mA IOH = -1mA IOH = -1.5mA IOH = -3mA IOH = -6mA 2.7 VDD 3.6V IOL = 1A IOL = 1mA IOL = 2mA IOL = 3mA IOL = 6mA IOL = 12mA 4.5 VDD 5.5V IOH = -1A IOH = -2mA IOH = -4mA IOH = -6mA IOH = -12mA IOH = -24mA 4.5 VDD 5.5V IOL = 1A IOL = 2mA IOL = 4mA IOL = 6mA IOL = 12mA IOL = 24mA
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Short Circuit Currents
All characteristics are for temperatures between -55 and 150C (junction temperature).
Characteristic
Symbol Min.
Value Typ. Max.
Unit
Conditions
Output short circuit current 01N 02N 03N 06N 12N Output short circuit current 01N 02N 03N 06N 12N Output short circuit current 01N 02N 03N 06N 12N Output short circuit current 01N 02N 03N 06N 12N IOS IOS IOS IOS IOS -3 -6 -9 -18 -36 -20 -35 -55 -95 -190 mA mA mA mA mA IOS IOS IOS IOS IOS 8 16 20 40 80 35 70 100 185 350 mA mA mA mA mA IOS IOS IOS IOS IOS -10 -20 -30 -55 -100 -36 -70 -100 -190 -340 mA mA mA mA mA IOS IOS IOS IOS IOS 20 40 50 100 190 60 120 160 300 560 mA mA mA mA mA
VDD = 5.5V VO = VDD
VDD = 5.5V VO = VSS
VDD = 3.6V VO = VDD
VDD = 3.6V VO = VSS
Operating Power
All characteristics are for temperatures between -55 and 150C (junction temperature).
VDD 3V 5V Operating Power (PDD) 0.5 W/MHz (note 1) 1.3 W/MHz (note 1)
Note 1: For NAND2 with two standard loads.
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CELL LIBRARY
I Comprehensive range of microcells I Extensive SystemBuilder library of complex functions I Software generated gate array RAM and high performance embedded RAM and ROM I Phase locked loop cells, both gate array variant and embedded variant with on-chip filter I Oscillator cells I 3.3V and 5V PCI/PC Card cells I JTAG controller (check availability) A comprehensive cell library is available for the CLA90000 series including cells for specific applications.
Gate Array ROM
Gate array ROM can be from 8 to 64 kbits with a word length of from 2 to 64 bits in steps of 1 bit. The table below shows memory sizes and typical access times for a ROM operatiing at 5V, 25C.
Read Access (ns) 2.61 3.40 4.24 Size gates 196 1440 5472 mm2 0.04 0.27 1.01
Size
24 words x 4 bits 256 words x 8bits 256 words x 64bits
Embedded RAM and ROM
The library is being continually expanded, so please check with your local Zarlink representative for the latest additions. Zarlink design kits feature a simple and powerful software tool called the paracell model generator (PMG) that can generate both gate array and embedded RAM. The design route is the same for both RAM types but the cost is different because an embedded RAM requires fabrication of all device layers. Embedded RAM and ROM meet requirements for high density and high performance. Word length can be from 4 to 64 bits and maximum memory size is 64 kbits for RAM and 128 kbits for ROM. The table below is for a typical embedded RAM operating at 5V, 25C.
Read Access (ns) 3.3 3.4 4.0 4.2 Write Cycle (ns) 3.7 3.9 4.7 5.8
Size
Size (mm2)
24 words x 4 bits 256 words x 8 bits
0.111 0.423 2.059 5.983
Register File RAM
Gate array RAM is available as either single or dual port RAM with a minimum size of 8 words x 2 bits and a maximum of 256 words x 64 bits. Memory speeds and number of gates uses are summarized in the table below for a typical single-port RAM operating at 5V, 25C.
Read Access (ns) 2.60 11.48 12.20 Write Cycle (ns) 3.21 6.31 11.22 Size gates 696 9918 53766 mm2 0.128 1.828 9.910
256 words x 64 bits 8192 words x 8 bits
The table below is for a typical embedded ROM operating at 5V, 25C.
Read Access (ns) 8.6 11.3 14.8 Read Cycle (ns) 11.1 14.9 18.1
Size
24 words x 4 bits 256 words x 8bits 256 words x 64bits
Size
Size (mm2)
256 words x 8 bits 256 words x 64 bits 4096 words x 16bits
0.215 0.827 1.638
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SystemBuilder Cells
Name M85C30 M82530 MFDC M765A M8051 M8237A M8042 M8048 M8254 M8253 M6845 M8251A M16C450 M146818 M8250B M8259A M8490 M91C360 M8255 M91C36 M8868A M6402 M8288 M82288 M82289 M82C84A M82C284 MxADD MxMPY MxBRL MxCOMP Function Two channel enhanced Serial Communications Controller (SCC) with FIFOs Two channel enhanced Serial Communications Controller (SCC) High performance PC-compatible floppy disk controller (82077SL) with M765A core Extended features floppy disk controller core for FM and MFM formats High performance industry-compatible 8-bit microcontroller, 2 timers, serial I/O General purpose programmable four channel DMA Controller 8-bit peripheral interface microcontroller with timer (slave microcontroller) Compact embedded industry-compatible 8-bit microcontroller with timer Extended feature three channel Programmable Interval Timer (PIT) General purpose three channel Programmable Interval Timer (PIT) General purpose programmable CRT Controller Universal Synchronous/Asynchronous Receiver/ Transmitter (USART) Universal Synchronous/Asynchronous Receiver/ Transmitter (UART) (PC-compatible) Ultra low power real-time clock with up to 114 bytes of RAM Universal Asynchronous Receiver/ Transmitter (UART) (PC-compatible) Eight channel cascadable Programmable Interrupt Controller (PIC) SCSI for 5380 compatible asynchronous SCSI interfacing High margin floppy and tape data separator for data rates up to 1.25Mbit/s General purpose Programmable Peripheral Interface (PPI) High margin floppy disk data separator for data rates up to 1.25Mbit/s Compact UART with configurable data formats Compact UART with configurable data formats Bus controller for 8086 and 8088 microprocessors Bus controller for 80286 microprocessors Bus arbiter for 80286 microprocessors, supports IEEE-796 Clock generator and ready I/F for 8086 and 8088 microprocessors Clock generator and ready I/F for 80286 microprocessors Fast adder set for 8, 16 and 32 bit DSP functions Multiplier set for 8x8, 16x16 and 32x32 bit DSP functions Barrel shifter set for 8, 16 and 32 bit DSP functions Comparator set for 4, 8, 16 and 32 bit DSP functions Approx. No. of Gates 18100 13400 11500 10200 *8700 4100 *3700 *3700 3600 3100 2900 2400 2200 *2200 2200 1800 1600 1400 1200 1200 840 830 270 230 200 70 70 140, 260 and 520 880, 3700 and 14300 80, 170 and 420 60, 100, 200 and 350
*Excluding RAM and ROM.
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AND Gates
Cell Name AND2 AND2X2 AND2X4 AND3 AND3X2 AND3X4 AND4 AND4X2 AND4X4 AND5 AND5X2 AND6 AND6X2 AND8 AND8X2 Cell Function 2-input AND x1drive 2-input AND x 2drive 2-input AND x4 drive 3-input AND x1 drive 3-input AND x2 drive 3-input AND x4 drive 4-input AND x1 drive 4-input AND x2 drive 4-input AND x4 drive 5-input AND x1 drive 5-input AND x2 drive 6-input AND x1 drive 6-input AND x2 drive 8-input AND x1 drive 8-input AND x2 drive
NAND Gates
Cell Name NAND2 NAND2X2 NAND2X4 NAND3 NAND3X2 NAND4 NAND4X2 NAND5 NAND5X2 NAND6 NAND6X2 NAND8 NAND8X2 Cell Function 2-input NAND x1 drive 2-input NAND x2 drive 2-input NAND x4 drive 3-input NAND x1 drive 3-input NAND x2 drive 4-input NAND x1 drive 4-input NAND x2 drive 5-input NAND x1 drive 5-input NAND x2 drive 6-input NAND x1 drive 6-input NAND x2 drive 8-input NAND x1 drive 8-input NAND x2 drive
NOR Gates
Cell Name Cell Function 2-input NOR x1 drive 2-input NOR x2 drive 2-input NOR x4 drive 3-input NOR x1 drive 3-input NOR x2 drive 4-input NOR x1 drive 4-input NOR x2 drive 5-input NOR x1 drive 5-input NOR x2 drive 6-input NOR x1 drive 6-input NOR x2 drive 8-input NOR x1 drive 8-input NOR x2 drive
OR Gates
Cell Name OR2 OR2X2 OR2X4 OR3 OR3X2 OR3X4 OR4 OR4X2 OR4X4 OR5 OR5X2 OR6 OR6X2 OR8 OR8X2 Cell Function 2-input OR x1 drive 2-input OR x2 drive 2-input OR x4 drive 3-input OR x1 drive 3-input OR x2 drive 3-input OR x4 drive 4-input OR x1 drive 4-input OR x2 drive 4-input OR x4 drive 5-input OR x1 drive 5-input OR x2 drive 6-input OR x1 drive 6-input OR x2 drive 8-input OR x1 drive 8-input OR x2 drive
NOR2 NOR2X2 NOR2X4 NOR3 NOR3X2 NOR4 NOR4X2 NOR5 NOR5X2 NOR6 NOR6X2 NOR8 NOR8X2
16
AND-OR-INVERTER Gates
Cell Name A2DO2I A2DO2IX2 A2O2I A2O2IX2 A2O3I A2O3IX2 A2DO3I A2DO3IX2 A3O2I A3O2IX2 A3DO2I A3DO2IX2 A2TO3I A2TO3IX2 AOAI AOAIX2 Cell Function 2-2 AOI x1 drive 2-2 AOI x2 drive 2-1 AOI x1 drive 2-1 AOI x2 drive 2-1-1 AOI x1 drive 2-1-1 AOI x2 drive 2-2-1 AOI x1 drive 2-2-1 AOI x2 drive 3-1 AOI x1 drive 3-1 AOI x2 drive 3-3 AOI x1 drive 3-3 AOI x2 drive 2-2-2 AOI x1 drive 2-2-2 AOI x2 drive AOAI x1 drive AOAI x2 drive
Exclusive OR and Adder Cells
Cell Name EXNOR EXNORX2 EXOR EXORX2 EXNOR3 EXNOR3X2 EXOR3 EXOR3X2 FADD FADDX2 FADD2 FADD2X2 HADD HADDX2 INCR DECR Cell Function Exclusive NOR x1 drive Exclusive NOR x2 drive Exclusive OR x1 drive Exclusive OR x2 drive 3-input Exclusive NOR x1 drive 3-input Exclusive NOR x2 drive 3-input Exclusive OR x1 drive 3-input Exclusive OR x2 drive Full adder x1 drive Full Adder x2 drive 2 bit Full adder x1 drive 2 bit Full adder x2 drive Half adder x1 drive Half adder x2 drive Increment x1 drive Decrement x1 drive
OR-AND-INVERTER Gates
Cell Name O2DA2I O2DA2IX2 O2A2I O2A2IX2 O2A3I O2A3IX2 O2DA3I O2DA3IX2 O3A2I O3A2IX2 O3DA2I O3DA2IX2 O2TA3I O2TA3IX2 OAOI OAOIX2 Cell Function 2-2 OAI x1 drive 2-2 OAI x2 drive 2-1 OAI x1 drive 2-1 OAI x2 drive 2-1-1 OAI x1 drive 2-1-1 OAI x2 drive 2-2-1 OAI x1 drive 2-2-1 OAI x2 drive 3-1 OAI x1 drive 3-1 OAI x2 drive 3-3 OAI x1 drive 3-3 OAI x2 drive 2-2-2 OAI x1 drive 2-2-2 OAI x2 drive OAOI x1 drive OAOI x2 drive
Noninverting Buffers
Cell Name BUFX1 BUFX3 BUFX7 Cell Function Noninverting buffer x1 drive Noninverting buffer x3 drive Noninverting buffer x7 drive
Inverting Buffers
Cell Name INVX1 INVX2 INVX4 INVX6 INVX8 Cell Function Inverting buffer x1 drive Inverting buffer x2 drive Inverting buffer x4 drive Inverting buffer x6 drive Inverting buffer x8 drive
17
Tristate Buffers
Cell Name Cell Function Tristate noninv buffer active low enable x1 drive
Special Cells
Cell Name DELAY Delay cell Bus hold 32kHz crystal oscillator 1MHz to 10MHz crystal oscillator 10MHz to 16MHz crystal oscillator 16MHz to 25MHz crystal oscillator Cell Function
BDRX1 BDRX2 BDRX4 BDRX8
BHOLD OSC32K OSCMID OSCHIGH OSCVHIGH
Tristate noninv buffer active low enable x2 drive Tristate noninv buffer active low enable x4 drive Tristate noninv buffer active low enable x8 drive
Multiplexers
Cell Name MUX2T1 MUX2T1X2 MUX4T1 MUX4T1X2 MUX8T1 MUX8T1X2 Cell Function 2-1 MUX non-inverting x1 drive 2-1 MUX non-inverting x2 drive 4-1 MUX non-inverting x1 drive 4-1 MUX non-inverting x2 drive 8-1 MUX non-inverting x1 drive 8-1 MUX non-inverting x2 drive
Phase Locked Loop Cells
Cell Name PLLC1M PLLC2M Cell Function Gate array phase locked loop Embedded phase locked loop with onchip filter
Memory Paracells
Cell Name Cell Function Single port register file memory Dual port register file memory Embedded single port RAM Embedded dual port RAM Embedded ROM Gate array ROM
D-type Flip-Flops
Cell Name SDF SDFS SDFR SDFRS SMDF SMDFS SMDFR SMDFRS DFF x1 drive DFF with SET x1 drive DFF with CLEAR x1 drive DFF with SET and CLEAR x1 drive MUX DFF x1 drive MUX DFF with SET x1 drive MUX DFF with CLEAR x1 drive MUX DFF with SET and CLEAR x1 drive Cell Function
SPRF DPRF MPRA MPDA MPRO HDRO
PCI/PC Card Cells
Cell Name PCIIO1 Cell Function 5V/3.3V I/O cell for 5V or mixed voltage device 3V I/O cell for 3V device 5V clock buffer for 5V or mixed voltage device 3V I/O cell for mixed voltage device 3V clock buffer for mixed voltage device
Transparent Latches
Cell Name SDL SDLR SMDL BDL BDLR BMDL SRLATCH Cell Function D latch active high enable x1 D latch with clear active high enable x1 Mux D latch active high enable x1 Buffered data latch Buffered data latch with reset MUX buffered D latch, active high enable Set reset latch
PCIIO2 PCICLK DNPCIIO1 DNPCICLK
18
I/O Cells
Cell Name ATSIrddN ACSIrddN 5V Core and 5V I/O 5V I/O, Schmitt input (TTL) 5V I/O, Schmitt input (CMOS)
PACKAGING
I Wide range of surface mount and through board packages I Various MQFP and ball grid array styles to international and JEDEC standards I Ceramic equivalents to most plastic packages for fast prototyping
Cell Name BBSIrddN
3V core and 3V I/O 3V I/O, Schmitt input (TTL/CMOS)
I Ongoing commitment to new package development
PACKAGING OPTIONS
Cell Name DTSIrddN DCSIrddN DBSIrddN DNSIrddN 3V core with 3V and 5V I/O 5V I/O, Schmitt input (TTL) 5V I/O, Schmitt input (CMOS) 3V I/O, Schmitt input (TTL/CMOS, low noise) 3V I/O, Schmitt input (TTL/CMOS, low power)
The package style and pin count information is intended only as a guide. Detailed package specifications are available from Zarlink Design Centres on request. New packages are being continually introduced, so if a particular package is not listed, please enquire through your Zarlink sales representative. The package dimensions implicit in the package Code,' pitch and height dimensions are approximate and for guidance only. If detailed information is required, an outline drawing will be provided on request. All package dimensions are in mm. A stock is held of the preferred packages to ensure a fast prototype assembly turn around. Alternative array size to package combinations are available, but not always stocked.
S means Schmitt input, I means inverting input. Each cell has three variations of resistor connection and five drive strength options as follows: Pullup, pulldown, or no resistor indicated by r=U, D, or N. Drive strength options indicated by dd=01, 02, 03, 06 or 12. The final N in the name means noninverting output. The cells can be used at other than 3 or 5 volts, but thresholds may then be out of specification.
I/O Cells
As the tables above show, the cell library contains an extensive range of I/Os, including cells for PCI/PC card applications. Each I/O cell occupies one I/O location and can be configured as an input, output or bidirectional, and has one pad associated with it. The output section of the I/O cell is configurable to one of four options: open drain, open source, tristate, or push-pull by suitable connection of the D and T inputs and each cell has a program pin that controls the slew rate of the output signal.
19
Key to packages,
1234 1234 1234 ^ 1234 * 1234 ^ = = = = = = Format number of preferred array/qualified package combination. Check availability with Zarlink. Check prototype package with Zarlink. In development. Maximum number of ceramic prototypes is 10 ONLY NO footprint compatible ceramic prototypes are available
High Density Pad Array Production Packages
Metric Quad Flat Pack - Plastic
Style Leads 44 52 64 64 M Q F P 64 80 80 100 120 128 144 160 Code MQFP44-GP-1010 MQFP52-GP-1010 MQFP64- GP-1420 MQFP64-GP-1414 MQFP64-GP-1414 MQFP80-GP-1420 MQFP80-GQ-1414 MQFP100-GP-1420 MQFP120-GP-2828 MQFP128-GP-2828 MQFP144-GP-2828 MQFP160-GP-2828 Pitch 0.80 0.65 1.00 0.80 0.80 0.80 0.65 0.65 0.80 0.80 0.65 0.65 Height 2.0 2.0 2.8 2.0 2.8 2.8 2.0 2.8 3.4 3.4 3.4 3.4 1835 2157^ 1807 2166 1730 1752^ 1835 2157 1808 2158 1730 1752 1835 2157 1808 2158 1899 2100 2159^ 1835 2157 1808 2158 1899 2100 2159 1882^ 1835 2157 1808 2158 1899 2100 2159 1882^ 2157 1808 2158 1899 2100 2159 1882^ 2157 1808 2158 1899 2100 2159 1882 901 1897 2155 1755 902 1897 2155 1755 903 1897 2155 1755 1755 1755 1755 2172 1755 2172 904 1897^ 905 1897^ 906 1897^ 907
Style
Leads 64
Code MQFP64-GP-1414 MQFP64-GP-1414 MQFP80-GP-1420 MQFP80-GQ-1414 MQFP100-GP-1420 MQFP120-GP-2828 MQFP128-GP-2828 MQFP144-GP-2828 MQFP160-GP-2828
Pitch 0.80 0.80 0.80 0.65 0.65 0.80 0.80 0.65 0.65
Height 2.0 2.8 2.8 2.0 2.8 3.4 3.4 3.4 3.4
908 2172
909 2172
910
911
912
913
914
M Q F P
64 80 80 100 120 128 144 160
1711 1808 2158 1899 2100 2159 1882
1711 1808 2158 1899 2100 2159 1882
1711^
1899 2100
1732
1732
1732
1882
1882
1882
2118
2118^
20
FQFP (Fine pitch) - Plastic
Style F Q F P Leads 100 208 Code FQFP100-FP-1414 FQFP208-FP-2828 Pitch 0.50 0.50 Height 2.0 3.4 901 1810 902 2156 903 2156 904 2156 905 2156 906 2156 2160^ 907 2156 2160^
Style F Q F P
Leads 100 208 240 304
Code FQFP100-FP-1414 FQFP208-FP-2828 FQFP240-FP-3232 FQFP304-FP-4040
Pitch 0.50 0.50 0.50 0.50
Height 2.0 3.4 3.4 3.8
908 2156 2160^ 2163^
909 2156 2160^ 2163^
910
911
912
913
914
2160 2163^
2160 2163^
2160 2163^ 3030
2160 2163 3030 2163 3030
LQFP (Low Profile) - Plastic
Style Leads 48 L Q F P 64 80 100 144 176 Code LQFP48-FP-0707 LQFP64-FP-1010 LQFP80-GP-1414 LQFP100-FP-1414 LQFP144-FP-2020 LQFP176-FP-2424 Pitch 0.50 0.50 0.65 0.50 0.50 0.50 Height 1.4 1.4 1.4 1.4 1.4 1.4 901 2168^ 2130 1889 1887 2164^ 902 2168^ 2130 1889 1887 2164^ 2130 1889 1887 2164^ 2165^ 2130 ^ 1889 1888 2164 2165^ 2130 ^ 1889 1888 2164 2165^ 1888 2164 2165^ 1888 2164 2165 2130 ^ 903 904 905 906 907
Style L Q F P
Leads
Code
Pitch
Height
908
909
910
911
912
913
914
100 144 176
LQFP100-FP-1414 LQFP144-FP-2020 LQFP176-FP-2424
0.50 0.50 0.50
1.4 1.4 1.4
1888 2237 2165
1888 2237 2165 2237 2165 2237^
21
P2QFP ('PowerQuad 2') - Plastic with Copper Heat Slug
Style Leads 100 P 2 Q F P 120 128 144 160 208 Code P2QFP100-GH-1420 P2QFP120-GH-2828 P2QFP128-GH-2828 P2QFP144-GH-2828 P2QFP160-GH-2828 P2QFP208-GH-2828 Pitch 0.65 0.80 0.80 0.65 0.65 0.50 Height 2.8 3.4 3.4 3.4 3.4 3.4 3002 2221 901 902 903 904 2202 3002 2221 2222 2223 905 2202 3002 2221 2222 2223 906 2202 3002 2221 2222 2223 907 2202 3002 2221 2222 2223 2225
Style
Leads 100
Code P2QFP100-GH-1420 P2QFP120-GH-2828 P2QFP128-GH-2828 P2QFP144-GH-2828 P2QFP160-GH-2828 P2QFP208-GH-2828 P2QFP240-GH-3232 P2QFP304-GH-4040
Pitch 0.65 0.80 0.80 0.65 0.65 0.50 0.50 0.50
Height 2.8 3.4 3.4 3.4 3.4 3.4 3.4 3.4
908
909
910
911
912
913
914
P 2 Q F P
120 128 144 160 208 240 304
3002 2221 2222 2223 2225 2228^
3002 2221 2222 2223 2225 2228^
2200 2221 2222 2223 2225 2228^
2200 2221 2222 2223 2225 2228^
2200 2221 2222 2223 2225 2228^
2200 2203 2226 2196 2225 2228
2200^ 2203 2226^ 2196^ 2225 2228
P4QFP ('PowerQuad 4') - Plastic with Copper Heat Slug
Style P 4 Q F P Leads 100 120 128 160 208 Code P4QFP100-GH-1420 P4QFP120-GH-2828 P4QFP128-GH-2828 P4QFP160-GH-2828 P4QFP208-GH-2828 Pitch 0.65 0.80 0.80 0.65 0.50 Height 2.8 3.37 3.42 3.37 3.49 901 902 2236 903 2236 3005 3008 904 2236 3005 3008 905 2236 3005 3008 3011 906 2236 3005 3008 3011 907 2236 3005 3008 3011 3014
Style
Leads 100
Code P4QFP100-GH-1420 P4QFP120-GH-2828 P4QFP128-GH-2828 P4QFP160-GH-2828 P4QFP208-GH-2828 P4QFP240-GH-3232 P4QFP304-GH-4040
Pitch 0.65 0.80 0.80 0.65 0.50 0.50 0.50
Height 2.8 3.37 3.42 3.37 3.49 3.4 3.8
908 2236 3006 3009 3011 3014 3017^
909 2236 3006 3009 3012 3014 3017^
910
911
912
913
914
P 4 Q F P
120 128 160 208 240 304
3006 3009 3012 3014 3017^
3006 3010 3012 3014 3017^
3006 3010 3012 3014 3016^ 3018^
3007 3010 3012 3015 3016 3018^
3007^ 3010 3013^ 3015 3016 3018^
22
BGA, Ball Grid Array - Plastic
Style P B G A Leads 169 225 313 352 Code PBGA169-BP-2323 PBGA225-BP-2727 PBGA313-BP-3535 PBGA352-BP-3535 Pitch 1.50 1.50 2.54 1.27 Height 2.09 2.09 2.29 2.29 901 902 903 904 905 906 907
Style P B G A
Leads 169 225 313 352
Code PBGA169-BP-2323 PBGA225-BP-2727 PBGA313-BP-3535 PBGA352-BP-3535
Pitch 1.50 1.50 2.54 1.27
Height 2.09 2.09 2.29 2.29
908
909
910
911
912
913
914

TQFP (Thin Profile) - Plastic
Style Leads 48 T Q F P 64 80 100 144 Code TQFP48-TP-0707 TQFP64-TP-1010 TQFP80-TP-1414 TQFP100-TP-1414 TQFP144-TP-2020 Pitch 0.50 0.50 0.50 0.50 0.50 Height 1.0 1.0 1.0 1.0 1.0 901 2117 902 2117 903 904 905 906 907
PLCC (Plastic J - Leaded Chip Carrier)
Style P L C C Leads 44 68 84 Code PLCC44-HP-1717 PLCC68-HP-2525 PLCC84-HP-3030 Pitch 1.27 1.27 1.27 Height 4.57 5.08 5.08 901 1491 1659 1660 902 1491 1659 1660 903 1491 1659 1660 904 1491 1659 1660 905 1491 1659 1660 1660 1660 906 1491 907 1491
23
High Density Pad Array Prototyping Packages
Important: CQFP/CBGA packages are intended for prototyping only. Production capability is available in special cases.
Prototypes for MQFPs and P2 & P4 MQFPs
Style Leads 44 52 64 C Q F P 64 80 80 100 120 128 144 160 Code CQFP44-GG-1010 CQFP52-GG-1010 CQFP64- GG-1420 CQFP64-GG-1414 CQFP80-GG-1420 CQFP80-GG-1414 CQFP100-GG-1420 CQFP120-GG-2828 CQFP128-GG-2828 CQFP144-GG-2828 CQFP160-GG-2828 Pitch 0.80 0.65 1.00 0.80 0.80 0.65 0.65 0.80 0.80 0.65 0.65 Height 3.2 3.2 2.8 2.8 2.8 2.8 2.8 3.6 3.6 3.6 3.6 2102* 1865* 1736* 901 1735* 1800* 1773* 2169* 902 1735* 1800* 1773* 2169* 1740* 2102* 1865* 1736* 1861* 903 1735* 1800* 1773* 2169* 1740* 2102* 1864* 1736* 1861* 1773* 2169* 1740* 2102* 1864* 1736* 1861* 1816* 1773 2169 1771 2102 1864 1736 1861 1816 1769 1772 2169 1771 1863 1864 1737 1861 1816 1769 1772 2169 1771 1863 1864 1737 1861 1816 1769 904 * 905 906 907
Style
Leads 64 80 80
Code CQFP64-GG-1414 CQFP80-GG-1420 CQFP80-GG-1414 CQFP100-GG-1420 CQFP120-GG-2828 CQFP128-GG-2828 CQFP144-GG-2828 CQFP160-GG-2828
Pitch 0.80 0.80 0.65 0.65 0.80 0.80 0.65 0.65
Height 2.8 2.8 2.8 2.8 3.6 3.6 3.6 3.6
908 2169 1779 1863 1864 1737 1726 1816 1769
909 2169 1779 1863 1864 1737 1726 1816 1769
910
911
912
913
914
C Q F P
100 120 128 144 160
1737 1726 1816 1769
1737 1726 1770 1769
1737 1726 1770 1769
1737 1726 1770 1769 1726
Prototypes for FQFP, LQFP and P2 & P4 MQFPs
Style C Q F P Leads 100 176 208 Code CQFP100-FG-1414 CQFP176-FG-2424 CQFP208-FG-2828 Pitch 0.50 0.50 0.50 Height 2.8 3.77 3.6 901 1860* 902 1860* 903 1860* 904 2101* 905 2101 2217 906 2101 2217 2217 2141 907
Style C Q F P
Leads 100 176 208 240
Code CQFP100-FG-1414 CQFP176-FG-2424 CQFP208-FG-2828 CQFP240-FG-2828
Pitch 0.50 0.50 0.50 0.50
Height 2.8 3.77 3.6 3.6
908 2101 2217 2141 2143
909 2101 2217 2141 2143
910
911
912
913
914
2217 2141 2143
2217 2141 2143
2217 2141 2143
2217 2141 2143 2141 2143
24
Prototypes for PLCC
Style C c L C C Leads 44 68 84 Code CcLCC44-HC-1717 CcLCC68-HC-2525 CcLCC84-HC-3030 Pitch 1.27 1.27 1.27 Height 3.43 3.43 3.43 901 1716 1621 1626 902 1716 1621 1626 903 1716 1621 1626 904 1716 1621 1626 905 1716 1621 1626 1473* 1473* 906 1716* 907 1716*
Prototypes for BGAs
Style C B G A Leads 169 225 313 352 Code CBGA169-BC-2323 CBGA225-BC-2727 CBGA313-BC-3535 CBGA352-BC-3535 Pitch 1.50 1.50 2.54 1.27 Height 2.09 2.09 2.29 2.29 901 902 903 904 905 906 907
Style C B G A
Leads 169 225 313 352
Code CBGA169-BC-2323 CBGA225-BC-2727 CBGA313-BC-3535 CBGA352-BC-3535
Pitch 1.50 1.50 2.54 1.27
Height 2.09 2.09 2.29 2.29
908
909
910
911
912
913
914

Prototypes for TQFPs
Style C Q F P Leads 64 80 100 144 Code CQFP64-FG-1010 CQFP80-GG-1414 CQFP100-FG-1414 CQFP144-FG-2020 Pitch 0.50 0.65 0.50 0.50 Height 3.2 2.8 2.8 3.6 901 2103* 2102* 1860* 902 2103* 2102* 1860* 903 2103* 2102* 1860* 904 * 2102* 2101* 2104 905 2102 2101 2104 906 1863 2101 2104 1863 907
25
Standard Density Pad Array Packages, Military Arrays LdCC
Style L d C C Leads 132 172 196 Code LdCC132-GCA-2424 LdCC172-GCA-3030 LdCC196-GCA-3535 Pitch 0.64 0.64 0.64 Height 2.57 2.82 2.82 901 1840 902 1840 903 1840 904 1840 905 1840 906 1840 1668 1672 907 1662 1668 1672
Style L d C C
Leads 132 172 196
Code LdCC132-GCA-2424 LdCC172-GCA-3030 LdCC196-GCA-3535
Pitch 0.64 0.64 0.64
Height 2.57 2.82 2.82
908 1662 1668 1672
909 1662 1668 1672
910 1662 1668 1672
911 1662 1668 1672
912 1662 1668 1672
913
914
1669 1672
1669 1831
LdCC & TLdCC - Power
Style L d C C T L d Leads 132 172 196 256 132 172 320 Code LdCC132-GCP-2424 LdCC172-GCP-3030 LdCC196-GCP-3535 LdCC256-GCP-3737 TLdCC132-YCP-2424 TLdCC172-YCP-3030 TLdCC320-YCP-4444 Pitch 0.64 0.64 0.64 0.51 0.62 0.62 0.5 Height 3.33 3.58 3.58 3.66 3.3 3.56 2.64 1839 901 902 903 904 905 906 907 1841 1836 1839
Style L d C C T L d
Leads 132 172 196 256 132 172 320
Code LdCC132-GCP-2424 LdCC172-GCP-3030 LdCC196-GCP-3535 LdCC256-GCP-3737 TLdCC132-YCP-2424 TLdCC172-YCP-3030 TLdCC320-YCP-4444
Pitch 0.64 0.64 0.64 0.51 0.62 0.62 0.5
Height 3.33 3.58 3.58 3.66 3.3 3.56 2.64
908 1841 1836 1839
909 1841 1836 1839
910 1841 1836 1839 1834
911 1841 1836 1839 1834 3023
912 1841 1836 1839 1834 3023
913
914
1762 1839 1834 3025 3027
1762 1739 1834 3025 3027 2206
3023
3023
2206
2206
2206
2206
2206
26
PGA
Style Leads 68 84 P G A 100 120 132 144 180 181 257 Code PGA68-ACA-2828 PGA84-ACA-2828 PGA100-ACA-3434 PGA120-ACA-3434 PGA132-ACA-3636 PGA144-ACA-4040 PGA180-ACA-4040 PGA181-ACA-4040 PGA257-ACA-5151 Pitch 2.54 2.54 2.54 2.54 2.54 2.54 2.54 2.54 2.54 Height 4.14 4.14 4.14 4.14 4.14 4.14 4.14 4.14 4.14 1484 901 1462 1479 902 1462 1479 903 1462 1479 1480 1481 904 1462 1479 1480 1481 1467 905 1462 1479 1480 1481 1467 1480 1481 1467 1480 1481 1467 1468 1484 2216 906 1463 907 1463
Style
Leads 100 120
Code PGA100-ACA-3434 PGA120-ACA-3434 PGA132-ACA-3636 PGA144-ACA-4040 PGA180-ACA-4040 PGA181-ACA-4040 PGA257-ACA-5151
Pitch 2.54 2.54 2.54 2.54 2.54 2.54 2.54
Height 4.14 4.14 4.14 4.14 4.14 4.14 4.14
908 1480 1481 1467 1468 1484 2216
909 1465 1466 1467 1468 1484 2216
910 1465 1466 1467 1468 1484 2216 1824
911 1465 1466
912
913
914
P G A
132 144 180 181 257
1468 1484 2216 1824
1468 1484 2216 1824
1468 1469 2216 1824 1844 1824
PGA, Power
Style P G A (P) Leads 84 144 208 209 Code PGA(P)84-ACB-2828 PGA(P)144-ACB-4040 PGA(P)208-ACB-4545 PGA(P)209-ACB-4545 Pitch 2.54 2.54 2.54 2.54 Height 6.15 6.15 4.45 4.45 1811 1811 2151 2151 2151 2151 901 902 903 904 905 2151 906 2151 907 1815 2151
Style P G A (P)
Leads 84 144 208 209
Code PGA(P)84-ACB-2828 PGA(P)144-ACB-4040 PGA(P)208-ACB-4545 PGA(P)209-ACB-4545
Pitch 2.54 2.54 2.54 2.54
Height 6.15 6.15 4.45 4.45
908 1815 1812
909 1815 1812
910 1815 1812 1838
911 1815 1812 1838 1811
912 1815 1812 1838 1811
913 1815 1693 1838
914
1693 1838
1811
1811
1811
27
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